In hierarchical VLSI circuit designs, design faults can be caused by electrically coupled capacitance between levels of hierarchy. To protect the design against the electrical capacitance coupling, electrically analyzing the hierarchical VLSI designs are required, however, that is challenging mostly due to the fact that allocated wiring resources between the levels of the hierarchy (also known as blockages) provide information for wiring or routing in the designs, but for the most part, lack information for electrical circuits therein. Thus, this will result in an inaccuracy in the noise analysis (e.g., pessimism) coupled with the blockages, and will cause to overpredict a coupled noise by the blockages and overdesign to compensate for the predicted coupled noise which may not really be as large as predicted over design on the VLSI circuit. Thus, a more efficient and accurate technique for analyzing a blockage coupled noise is needed.